1. Field of the Invention
This invention concerns semiconductor integrated circuits and a fabrication method thereof and, more in particular, it relates to a technique effective to be applied to semiconductor integrated circuits having DRAM (Dynamic Random Access Memory).
2. Description of the Prior Art
DRAM is constituted by arranging memory cells each comprising a selection transistor and information storage capacitor (hereinafter referred to as a capacitor) connected therewith in a matrix form on a semiconductor substrate. For constituting DRAM of an increased capacitance, densification of the static capacitance of the memory cell capacitor is necessary. As the technique therefor Japanese Patent Laid-open No.HEI 06-244364, for example, discloses a method of using tantalum pentaoxide having a high dielectric constant for the dielectric film of the capacitor. In this conventional technique, a silicon nitride film is formed on the surface of polycrystal silicon as an electrode by a thermal nitridation method using ammonia to prevent oxidation of the electrode upon heat treatment of the tantalum pentaoxide film in an oxygen atmosphere. Further, Japanese Patent Laid-open No.HEI 11-26712, for example, discloses a conventional technique of forming semi-spherical silicon oxide crystal on the surface of a polycrystal silicon electrode, forming silicon nitride film and tantalum pentaoxide in the same manner to constitute a capacitor. According to the conventional technique, static capacitance can be enlarged due to high dielectric constant of tantalum pentaoxide and increase in the effective electrode surface with the semi-spherical silicon crystal.
The present inventors have made a study on the capacitor for use in DRAM for the semiconductor integrated circuits of enlarged capacitance such as DRAM of 256 Mbits or 1 Gbit.
In the capacitor process, when thermal nitridation was conducted at 800xc2x0 C. using ammonia, oxidation of the silicon nitride film occurs during the heat treatment for crystallization of tantalum pentaoxide (800xc2x0 C. in oxygen), to lower the capacitance of the capacitor. Generally, as the reference of the capacitance density of a capacitor, a film thickness equivalent to a silicon oxide film having a relative of 3.9 dielectric constant is used. Reduction of the equivalent thickness means increase in the capacitance density of the capacitor.
In the case mentioned above, the equivalent thickness of the capacitor after the crystallization treatment was 3.3 nm (effective equivalent thickness of capacitor is 1.65 nm since the effective electrode surface area can be doubled by the semi-spherical silicon crystal). Then, the application limit of the capacitor has been studied. For preventing soft errors and preventing reading errors, the capacitance of a capacitor to be stored in the capacitor per 1 bit should be at least 25 fF or more. FIG. 9 shows a relation between the feature size of capacitors and the aspect ratio of a storage node for attaining 25 fF of capacitor capacitance per 1 bit (ratio between the storage node height and the feature size). It was compared for the equivalent thickness of the capacitor of 1.5 nm, 2.0 nm, 2.5 nm and 3.0 nm, and conventional 3.3 nm, respectively. The fabrication limit for preparing a rugged storage node by the application of the semi-spherical silicon crystal was at an aspect ratio of 15 in view of the yield. That is, when the feature size is 0.13 xcexcm, the height of the storage node is 2.0 xcexcm. It can be seen from FIG. 9 that the capacitor having 3.3 nm of equivalent thickness has an application limit in DRAM having a feature size of 0.16 xcexcm. For attaining DRAM of higher speed and enlarged capacitance, the fabrication feature should be further reduced to 0.15 xcexcm or less. For this purpose, the equivalent thickness of capacitor has to be reduced at least to 3.0 nm or less as can be seen from FIG. 9.
The present inventors have further analyzed the capacitor in details. The temperature necessary for the crystallization of tantalum pentaoxide is at least 700xc2x0 C. By the crystallization, tantalum pentaoxide crystallizes from an amorphous structure with a relative dielectric constant of 25 into a xcex4-phase structure the relative dielectric constant increased to 40-60. However, since crystallization and oxidation of the silicon nitride film occur concurrently, the effect of increasing the dielectric constant was offset by the lowering of the capacitance due to oxidation of the silicon nitride film. When the temperature of heat treatment for crystallization was lowered to 700xc2x0 C., oxidation of the silicon nitride film could be suppressed somewhat and the equivalent thickness could be reduced to 3.1 nm, but this resulted in a problem of increasing the leakage current density. When the leakage current of the capacitor is large, since the time till the loss of once stored information is shortened, the refresh time up to writing of the information once more is shortened to hinder high speed operation. As a threshold value, the leakage current should be 1 fA or less when a voltage of 1 V is added per 1 bit.
This invention intends to provide a capacitor having a capacitance density of a capacitor with a thickness equivalent to a silicon oxide film being 3.0 nm or less and with a leakage current of 1 fA or less upon application of a positive bias of 1 V per 1 bit on a rugged polycrystal silicon electrode, required for the fine semiconductor integrated circuits as described above.
The semiconductor integrated circuit according to this invention has a capacitor comprising a lower electrode having a polycrystal silicon film and semi-spherical silicon crystals formed on the surface thereof, a first dielectric film of 2.5 nm or more of physical thickness in contact with the lower electrode and a second dielectric film made of tantalum pentaoxide. The first dielectric film is a film of 2.5 nm or more capable of suppressing tunneling of electron from the inside of the polycrystal silicon film into tantalum pentaoxide. The film can include, for example, Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4. HfSiO4, a mixed phase of Y2O3 and SiO2, a mixed phase of La2O3 and SiO2 and a silicon nitride film.
The effect of capacitors formed by applying the interface films as a feature of this invention is to be explained with reference to FIG. 1.
FIG. 1A shows a relation of film thickness for the thickness of the interface film and the thickness of the tantalum pentaoxide after completion of capacitors where the leakage current of capacitors is 1 fA or less when the positive bias of 1 V is applied to the plate electrode. All of the capacitors are applied with thermal treatment for crystallization in oxygen at 750xc2x0 C. for 5 min. It can be seen from FIG. 1A that the thickness of tantalum pentaoxide required to suppress the leakage current to 1 fA or less (when the positive bias of 1 V is applied to the plate electrode) increases abruptly as the interface thickness is decreased. Further, it can also be seen that the trend does not depend on the interfacial film. For making the equivalent thickness of capacitor thin, it is simply considered that reduction of the thickness of the interfacial film of low dielectric constant is important. However, the result of FIG. 1(a) shows that a substantial lower limit exists for the interfacial film thickness in order to suppress the leakage current.
FIG. 1B shows a relation between the equivalent thickness and the interfacial thickness of capacitors having the thickness for the interfacial film and the tantalum pentaoxide shown in FIG. 1A. The abscissa indicates the thickness of the interfacial film after completion of the capacitor. The ordinate indicates a result of measurement for the equivalent thickness of capacitor having the thickness of the tantalum pentaoxide given by FIG. 1A. It can be seen that along with increase in the interfacial thickness, the equivalent thickness once shows a minimum value and then turns to increase. The equivalent film thickness of all capacitors is lowered with all the increase of the interfacial thickness, because the thickness of the tantalum pentaoxide necessary for the suppression of the leakage current is decreased remarkably. From, FIG. 1, it can be seen that the interfacial thickness should be at least 2.5 nm or more in order to suppress the leakage current and restrict the equivalent thickness to 3.0 nm or less.
Further, as shown in FIG. 1B, the equivalent thickness shows a minimum value at a certain interfacial thickness. The value for the minimum equivalent thickness is different depending on the interfacial film. Particularly, the equivalent thickness of capacitors can be reduced to about 2.0 nm by using Al2O3, ZrSiO4 or HfSiO4. The value is smaller by 1.0 nm or more compared with 3.3 nm that can be realized by the conventional technique. For the method of forming the interfacial film, it is preferred to adopt an atom layer deposition (ALD) method having a feature capable of precisely controlling the deposition thickness and forming a conformal film. Further, it has been found that the equivalent thickness of capacitor can be made thin as low as 2.7 nm also by previously forming the silicon nitride film of 2.5 nm or more, for example, by an LPCVD method.
Characteristics of the tantalum pentaoxide capacitor described above can be explained by the following mechanism based on the state of band shown in FIG. 8. The leakage current in the tantalum pentaoxide capacitor now studied in which the total thickness of the insulative films is less than 20 nm depends on the probability at which electrons are injected from a polycrystal silicon electrode into tantalum pentaoxide. Further, as shown in FIG. 1A, the film thickness of tantalum pentaoxide required for suppressing the leakage current increases remarkably at the interfacial thickness of 2.5 nm as a boundary. It can be seen from the foregoings that the tunneling current in the tantalum pentaoxide capacitor is determined by the interfacial film. The tunneling probability of the interfacial film is determined by the barrier height V1 and the tunneling distance t of the interfacial film relative to electrons in the polycrystal silicon electrode. A film of higher dielectric constant generally has a lower barrier height and the tunneling probability is high when compared with respect to the identical film thickness. A film having a higher barrier height than the barrier height of tantalum pentaoxide to silicon (1.5 eV) is a candidate for the interfacial film. Further, it is desirable for a interfacial film with a lower formation energy of oxide than that of the silicon oxide film for suppressing the oxidation of the lower silicon electrode. The barrier height of any of such interfacial films is lower compared with 3.1 eV of the silicon oxide film. The formula for the direct tunneling current of the interfacial film is shown, for example, in S. M. Sze: Physics of Semiconductor devices (Wiley, N.Y., 1981), p. 553-557.
The tunneling probability when a positive bias voltage +Va (V) is applied to the plate electrode decreases exponentially relative to the tunneling distance, and it decreases exponentially relative to (V1xe2x88x92Va/2)0.5 with respect to the barrier height. This shows that the dependency on the barrier height is smaller than that on the film thickness. Accordingly, it is considered that a lower limit for the interfacial thickness exists in order to obtain a capacitor of low leakage current. In addition, since the tantalum pentaoxide film can be made remarkably thin by a slight increase in the thickness of the interfacial film as shown in FIG. 1B, this can lead to a result that the equivalent thickness can be made thin as the thickness of the interfacial film is large with a certain range regarding the equivalent thickness of the entire capacitor. Accordingly, it is considered that a substantial lower limit exists for the interfacial thickness also in order to obtain a tantalum pentaoxide capacitor of reduced equivalent thickness. The thickness of the capacitor can be made thin compared with the conventional technique, because a film having a higher relative dielectric constant of the interfacial film compared with that of the nitride film (actually, oxynitride film approximate to oxide film) can be selected. Since the interfacial layers have lower value compared with the silicon oxide film, it is necessary to make the film thick in order to decrease the leakage current. However, since the relative dielectric constant is high, it is advantageous to apply such interfacial films. On the other hand, the equivalent film thickness turns to increase at a certain interfacial thickness as a boundary, because it is considered that a large electric field is concentrated to the interfacial film and it transfers from the direct tunneling current characteristics to a large leakage current in an FN tunneling manner.
On the other hand, the leakage current, when a negative voltage is applied to the plate electrode, is mainly determined depending on the height of the Schottky barrier formed between the tantalum pentaoxide and the titanium nitride upper electrode. As the capacitance of the interfacial film is larger, electric field exerting on tantalum pentaoxide increases, so that the leakage current increases. However, so long as the interfacial film described above is concerned, the leakage current is sufficiently low and causes no problems. In a case where the leakage current is intended to be lowered further, a metal such as ruthenium having a larger work function than the titanium nitride may also be used as the upper electrode.